LM3S8G62 Datasheet, PDF (824/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bit/Field
31:7
6
Name
reserved
PHYINTM
Type
RO
R/W
Reset
0
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask PHY Interrupt
Value Description
1 An interrupt is sent to the interrupt controller when the PHYINT
bit in the MACRIS/MACIACK register is set.
0 The PHYINT interrupt is suppressed and not sent to the interrupt
controller.
5
MDINTM
R/W
1
Mask MII Transaction Complete
Value Description
1 An interrupt is sent to the interrupt controller when the MDINT
bit in the MACRIS/MACIACK register is set.
0 The MDINT interrupt is suppressed and not sent to the interrupt
controller.
4
RXERM
R/W
1
Mask Receive Error
Value Description
1 An interrupt is sent to the interrupt controller when the RXER bit
in the MACRIS/MACIACK register is set.
0 The RXER interrupt is suppressed and not sent to the interrupt
controller.
824
July 24, 2012
Texas Instruments-Production Data