LM3S8G62 Datasheet, PDF (13/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Figure 17-2. Ethernet Controller Block Diagram ...................................................................... 808
Figure 17-3. Ethernet Frame ................................................................................................. 810
Figure 17-4. Interface to an Ethernet Jack .............................................................................. 817
Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 866
Figure 18-2. Structure of Comparator Unit .............................................................................. 868
Figure 18-3. Comparator Internal Reference Structure ............................................................ 868
Figure 19-1. PWM Module Diagram ....................................................................................... 880
Figure 19-2. PWM Generator Block Diagram .......................................................................... 880
Figure 19-3. PWM Count-Down Mode .................................................................................... 883
Figure 19-4. PWM Count-Up/Down Mode .............................................................................. 884
Figure 19-5. PWM Generation Example In Count-Up/Down Mode ........................................... 884
Figure 19-6. PWM Dead-Band Generator ............................................................................... 885
Figure 20-1. QEI Block Diagram ............................................................................................ 951
Figure 20-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 953
Figure 21-1. 100-Pin LQFP Package Pin Diagram .................................................................. 973
Figure 21-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 974
Figure 24-1. Load Conditions ............................................................................................... 1032
Figure 24-2. JTAG Test Clock Input Timing ........................................................................... 1033
Figure 24-3. JTAG Test Access Port (TAP) Timing ................................................................ 1033
Figure 24-4. Power-On Reset Timing ................................................................................... 1034
Figure 24-5. Brown-Out Reset Timing .................................................................................. 1034
Figure 24-6. Power-On Reset and Voltage Parameters ......................................................... 1035
Figure 24-7. External Reset Timing (RST) ............................................................................ 1035
Figure 24-8. Software Reset Timing ..................................................................................... 1035
Figure 24-9. Watchdog Reset Timing ................................................................................... 1036
Figure 24-10. MOSC Failure Reset Timing ............................................................................. 1036
Figure 24-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation .......... 1040
Figure 24-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation .......... 1041
Figure 24-13. ADC Input Equivalency Diagram ....................................................................... 1043
Figure 24-14. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1044
Figure 24-15. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1044
Figure 24-16. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1045
Figure 24-17. I²C Timing ....................................................................................................... 1046
Figure 24-18. External XTLP Oscillator Characteristics ........................................................... 1048
Figure C-1. Stellaris LM3S8G62 100-Pin LQFP Package Dimensions ................................... 1087
Figure C-2. 100-Pin LQFP Tray Dimensions ........................................................................ 1089
Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1090
Figure C-4. Stellaris LM3S8G62 108-Ball BGA Package Dimensions .................................... 1091
Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1093
Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1094
July 24, 2012
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Texas Instruments-Production Data