LM3S8G62 Datasheet, PDF (625/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
13.3.10
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the LBE bit in the UARTCTL register (see page 642). In loopback mode, data transmitted on the
UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is
enabled.
13.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation
and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion
interrupt.
See “Micro Direct Memory Access (μDMA)” on page 349 for more details about programming the
μDMA controller.
13.4
Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. The peripheral clock must be enabled by setting the UART0 or UART1 bits in the RCGC1
register (see page 256).
2. The clock to the appropriate GPIO module must be enabled via the RCGC2 register in the
System Control module (see page 265).
3. Set the GPIO AFSEL bits for the appropriate pins (see page 431). To determine which GPIOs to
configure, see Table 22-4 on page 991.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 433 and page 441).
July 24, 2012
625
Texas Instruments-Production Data