LM3S8G62 Datasheet, PDF (14/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Table of Contents
OBSOLETE: TI has discontinued production of this device.
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 30
Documentation Conventions ................................................................................ 33
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 61
Processor Register Map ....................................................................................... 62
PSR Register Combinations ................................................................................. 67
Memory Map ....................................................................................................... 75
Memory Access Behavior ..................................................................................... 78
SRAM Memory Bit-Banding Regions .................................................................... 80
Peripheral Memory Bit-Banding Regions ............................................................... 80
Exception Types .................................................................................................. 86
Interrupts ............................................................................................................ 86
Exception Return Behavior ................................................................................... 91
Faults ................................................................................................................. 92
Fault Status and Fault Address Registers .............................................................. 93
Cortex-M3 Instruction Summary ........................................................................... 95
Core Peripheral Register Regions ......................................................................... 99
Memory Attributes Summary .............................................................................. 102
TEX, S, C, and B Bit Field Encoding ................................................................... 105
Cache Policy for Memory Attribute Encoding ....................................................... 106
AP Bit Field Encoding ........................................................................................ 106
Memory Region Attributes for Stellaris Microcontrollers ........................................ 106
Peripherals Register Map ................................................................................... 107
Interrupt Priority Levels ...................................................................................... 134
Example SIZE Field Values ................................................................................ 162
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 166
JTAG_SWD_SWO Signals (108BGA) ................................................................. 167
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 168
JTAG Instruction Register Commands ................................................................. 173
System Control & Clocks Signals (100LQFP) ...................................................... 177
System Control & Clocks Signals (108BGA) ........................................................ 177
Reset Sources ................................................................................................... 178
Clock Source Options ........................................................................................ 185
Possible System Clock Frequencies Using the SYSDIV Field ............................... 188
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 188
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 189
System Control Register Map ............................................................................. 193
RCC2 Fields that Override RCC Fields ............................................................... 214
Hibernate Signals (100LQFP) ............................................................................. 278
Hibernate Signals (108BGA) .............................................................................. 279
Hibernation Module Clock Operation ................................................................... 285
Hibernation Module Register Map ....................................................................... 287
Flash Memory Protection Policy Combinations .................................................... 308
User-Programmable Flash Memory Resident Registers ....................................... 312
Flash Register Map ............................................................................................ 312
μDMA Channel Assignments .............................................................................. 351
Request Type Support ....................................................................................... 353
14
July 24, 2012
Texas Instruments-Production Data