LM3S8G62 Datasheet, PDF (663/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Register 15: UART LIN Control (UARTLCTL), offset 0x090
The UARTLCTL register is the configures the operation of the UART when in LIN mode.
UART LIN Control (UARTLCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x090
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BLEN
reserved
MASTER
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5:4
Name
reserved
BLEN
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
Sync Break Length
Value Description
0x3 Sync break length is 16T bits
0x2 Sync break length is 15T bits
0x1 Sync break length is 14T bits
0x0 Sync break length is 13T bits (default)
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MASTER
R/W
0
LIN Master Enable
Value Description
1 The UART operates as a LIN master.
0 The UART operates as a LIN slave.
July 24, 2012
663
Texas Instruments-Production Data