LM3S8G62 Datasheet, PDF (686/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Synchronous Serial Interface (SSI)
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words,
and termination is the same as that of the single word transfer.
14.3.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 14-7 on page 686 and Figure 14-8 on page 686.
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
MSB
MSB
4 to 16 bits
LSB
Q
LSB
Note: Q is undefined.
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx _LSB
MSB
LSB
4 to 16 bits
MSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low, causing slave data to be immediately transferred onto
the SSIRx line of the master. The master SSITx output pad is enabled.
One-half period later, valid master data is transferred to the SSITx line. Once both the master and
slave data have been set, the SSIClk master clock pin becomes Low after one additional half
SSIClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
686
July 24, 2012
Texas Instruments-Production Data