LM3S8G62 Datasheet, PDF (887/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
19.3.8
The PWM generator can use the following inputs to generate a fault condition, including:
■ FAULTn pin assertion
■ A stall of the controller generated by the debugger
■ The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures
the necessary conditions to indicate a fault condition exists. This method allows the development
of applications with dependent and independent control.
Four fault input pins (FAULT0-FAULT3) are available. These inputs may be used with circuits that
generate an active High or active Low signal to indicate an error condition. A FAULTn pins may be
individually programmed for the appropriate logic sense using the PWMnFLTSEN register.
The PWM generator's mode control, including fault condition handling, is provided in the PWMnCTL
register. This register determines whether the input or a combination of FAULTn input signals and/or
digital comparator triggers (as configured by the PWMnFLTSRC0 and PWMnFLTSRC1 registers)
is used to generate a fault condition. The PWMnCTL register also selects whether the fault condition
is maintained as long as the external condition lasts or if it is latched until the fault condition until
cleared by software. Finally, this register also enables a counter that may be used to extend the
period of a fault condition for external events to assure that the duration is a minimum length. The
minimum fault period count is specified in the PWMnMINFLTPER register.
Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1
registers.
PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN
register.
Output Control Block
The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before
they go to the pins as the PWMn signals. Via a single register, the PWM Output Enable
(PWNENABLE) register, the set of PWM signals that are actually enabled to the pins can be modified.
This function can be used, for example, to perform commutation of a brushless DC motor with a
single register write (and without modifying the individual PWM generators, which are modified by
the feedback control loop). In addition, the updating of the bits in the PWMENABLE register can
be configured to be immediate or locally or globally synchronized to the next synchronous update
using the PWM Enable Update (PWMENUPD) register.
During fault conditions, the PWM output signals, PWMn, usually must be driven to safe values so
that external equipment may be safely controlled. The PWMFAULT register specifies whether during
a fault condition, the generated signal continues to be passed driven or to an encoding specified in
the PWMFAULTVAL register.
A final inversion can be applied to any of the PWMn signals, making them active Low instead of the
default active High using the PWM Output Inversion (PWMINVERT). The inversion is applied even
if a value has been enabled in the PWMFAULT register and specified in the PWMFAULTVAL
register. In other words, if a bit is set in the PWMFAULT, PWMFAULTVAL, and PWMINVERT
registers, the output on the PWMn signal is 0, not 1 as specified in the PWMFAULTVAL register.
July 24, 2012
887
Texas Instruments-Production Data