LM3S8G62 Datasheet, PDF (658/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
5
4
3
2
1
Name
TXMIS
RXMIS
DSRMIS
DCDMIS
CTSMIS
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
UART Transmit Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
UART Receive Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
UART Data Set Ready Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Data Set Ready.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0.
UART Data Carrier Detect Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Data Carrier Detect.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0.
UART Clear to Send Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Clear to Send.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0.
658
July 24, 2012
Texas Instruments-Production Data