LM3S8G62 Datasheet, PDF (1005/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Table 22-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PB3
I/O
TTL
GPIO port B bit 3.
Fault0
C12
Fault3
I2C0SDA
I
TTL
PWM Fault 0.
I
TTL
PWM Fault 3.
I/O
OD
I²C module 0 data.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
D3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 24-6 on page 1036 .
D10
VDD
-
Power Positive supply for I/O and some logic.
D11
VDD
-
Power Positive supply for I/O and some logic.
PB1
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
D12
CCP2
PWM3
I/O
TTL
Capture/Compare/PWM 2.
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
E1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
E2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
E10
VDD
-
Power Positive supply for I/O and some logic.
E11
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
CCP0
E12
PWM2
I/O
TTL
Capture/Compare/PWM 0.
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
F1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
F2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
F3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 24-6 on page 1036 .
F10
GND
-
Power Ground reference for logic and I/O pins.
F11
GND
-
Power Ground reference for logic and I/O pins.
F12
GND
-
Power Ground reference for logic and I/O pins.
July 24, 2012
Texas Instruments-Production Data
1005