LM3S8G62 Datasheet, PDF (5/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
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Hibernation Module .............................................................................................. 277
6.1 Block Diagram ............................................................................................................ 278
6.2 Signal Description ....................................................................................................... 278
6.3 Functional Description ................................................................................................. 279
6.3.1 Register Access Timing ............................................................................................... 279
6.3.2 Hibernation Clock Source ............................................................................................ 280
6.3.3 System Implementation ............................................................................................... 281
6.3.4 Battery Management ................................................................................................... 282
6.3.5 Real-Time Clock .......................................................................................................... 282
6.3.6 Battery-Backed Memory .............................................................................................. 283
6.3.7 Power Control Using HIB ............................................................................................. 283
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 283
6.3.9 Initiating Hibernate ...................................................................................................... 283
6.3.10 Waking from Hibernate ................................................................................................ 283
6.3.11 Interrupts and Status ................................................................................................... 284
6.4 Initialization and Configuration ..................................................................................... 284
6.4.1 Initialization ................................................................................................................. 284
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 285
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 285
6.4.4 External Wake-Up from Hibernation .............................................................................. 286
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 286
6.5 Register Map .............................................................................................................. 286
6.6 Register Descriptions .................................................................................................. 287
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 304
Block Diagram ............................................................................................................ 304
Functional Description ................................................................................................. 304
SRAM ........................................................................................................................ 305
ROM .......................................................................................................................... 305
Flash Memory ............................................................................................................. 307
Register Map .............................................................................................................. 312
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 313
Memory Register Descriptions (System Control Offset) .................................................. 325
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Micro Direct Memory Access (μDMA) ................................................................ 349
8.1 Block Diagram ............................................................................................................ 350
8.2 Functional Description ................................................................................................. 350
8.2.1 Channel Assignments .................................................................................................. 351
8.2.2 Priority ........................................................................................................................ 352
8.2.3 Arbitration Size ............................................................................................................ 352
8.2.4 Request Types ............................................................................................................ 352
8.2.5 Channel Configuration ................................................................................................. 353
8.2.6 Transfer Modes ........................................................................................................... 355
8.2.7 Transfer Size and Increment ........................................................................................ 363
8.2.8 Peripheral Interface ..................................................................................................... 363
8.2.9 Software Request ........................................................................................................ 363
8.2.10 Interrupts and Errors .................................................................................................... 364
8.3 Initialization and Configuration ..................................................................................... 364
8.3.1 Module Initialization ..................................................................................................... 364
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 365
July 24, 2012
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