LM3S8G62 Datasheet, PDF (846/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY layer. The default settings of
these registers are designed to initialize the Ethernet Controller to a normal operational mode without
configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x1000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
15
14
Name
RESET
LOOPBK
Type
R/W
R/W
Reset
0
0
Description
Reset Registers
Value Description
1 The PHY layer registers reset to their default state and the
internal state machines are reinitialized.
0 No effect.
Once the reset operation has completed, this bit is automatically cleared
by hardware.
Loopback Mode
Value Description
1 Enables the Loopback mode of operation. The receiver ignores
external inputs and receives the data that is transmitted by the
transmitter.
0 No effect.
13
SPEEDSL
R/W
0
Speed Select
Value Description
1 Enables the 100 Mbps mode of operation (100BASE-TX).
0 Enables the 10 Mbps mode of operation (10BASE-T).
12
ANEGEN
R/W
1
Auto-Negotiation Enable
Value Description
1 Enables the auto-negotiation process.
0 No effect.
846
July 24, 2012
Texas Instruments-Production Data