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LM3S8G62 Datasheet, PDF (46/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller | |||
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OBSOLETE: TI has discontinued production of this device.
Architectural Overview
1.3.4.2
â ARM PrimeCell® 32-channel configurable µDMA controller
â Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
â Basic for simple transfer scenarios
â Ping-pong for continuous data flow
â Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
â Highly flexible and configurable channel operation
â Independently configured and operated channels
â Dedicated channels for supported on-chip modules
â Primary and secondary channel assignments
â One channel each for receive and transmit path for bidirectional modules
â Dedicated channel for software-initiated transfers
â Per-channel configurable priority scheme
â Optional software-initiated requests for any channel
â Two levels of priority
â Design optimizations for improved bus access performance between µDMA controller and the
processor core
â µDMA controller access is subordinate to core access
â RAM striping
â Peripheral bus segmentation
â Data sizes of 8, 16, and 32 bits
â Transfer size is programmable in binary steps from 1 to 1024
â Source and destination address increment size of byte, half-word, word, or no increment
â Maskable peripheral requests
â Interrupt on transfer completion, with a separate interrupt per channel
System Control and Clocks (see page 177)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
â Device identification information: version, part number, SRAM size, Flash memory size, and so
on
46
July 24, 2012
Texas Instruments-Production Data
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