PIC18F23K22 Datasheet, PDF (70/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES
PC<20:0>
CALL,RCALL,RETURN
21
RETFIE,RETLW
Stack Level 1



Stack Level 31
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
On-Chip
Program Memory
1FFFh
2000h
On-Chip
Program Memory
PIC18(L)F23K22
PIC18(L)F43K22
3FFFh
4000h
PIC18(L)F24K22
On-Chip
Program Memory
PIC18(L)F44K22
7FFFh
8000h
On-Chip
Program Memory
0000h
0008h
0018h
Read ‘0’
Read ‘0’
PIC18(L)F25K22
PIC18(L)F45K22
Read ‘0’
FFFFh
10000h
PIC18(L)F26K22
PIC18(L)F46K22
Read ‘0’
1FFFFFh
200000h
5.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
DS41412B-page 70
Preliminary
 2010 Microchip Technology Inc.