PIC18F23K22 Datasheet, PDF(25/492 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18F23K22 Datasheet, PDF (25/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18(L)F2X/4XK22

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

PDIP TQFP QFN

Pin Name

Pin Buffer

Type Type

Description

21 40

40 RD2/P2B/AN22

RD2

P2B(1)

I/O

TTL Digital I/O

O CMOS Enhanced CCP2 PWM output.

AN22

I Analog Analog input 22.

22 41

41 RD3/P2C/SS2/AN23

RD3

I/O

TTL Digital I/O.

P2C

O CMOS Enhanced CCP2 PWM output.

SS2

I

TTL SPI slave select input (MSSP2).

AN23

I Analog Analog input 23.

27

2

2 RD4/P2D/SDO2/AN24

RD4

I/O

TTL Digital I/O.

P2D

O CMOS Enhanced CCP2 PWM output.

SDO2

O

â SPI data out (MSSP2).

AN24

I Analog Analog input 24.

28

3

3 RD5/P1B/AN25

RD5

I/O

TTL Digital I/O.

P1B

O CMOS Enhanced CCP1 PWM output.

AN25

I Analog Analog input 25.

29

4

4 RD6/P1C/TX2/CK2/AN26

RD6

I/O

TTL Digital I/O.

P1C

O CMOS Enhanced CCP1 PWM output.

TX2

O

â EUSART 2 asynchronous transmit.

CK2

I/O

ST EUSART 2 synchronous clock (see related RXx/

DTx).

AN26

I Analog Analog input 26.

30

5

5 RD7/P1D/RX2/DT2/AN27

RD7

I/O

TTL Digital I/O.

P1D

O CMOS Enhanced CCP1 PWM output.

RX2

I

ST EUSART 2 asynchronous receive.

DT2

I/O

ST EUSART 2 synchronous data (see related TXx/

CKx).

AN27

I Analog Analog input 27.

8

25

25 RE0/P3A/CCP3/AN5

RE0

P3A(2)

CCP3(2)

I/O

TTL Digital I/O.

O CMOS Enhanced CCP3 PWM output.

I/O

ST Capture 3 input/Compare 3 output/PWM 3 output.

AN5

I Analog Analog input 5.

9

26

26 RE1/P3B/AN6

RE1

I/O

TTL Digital I/O.

P3B

O CMOS Enhanced CCP3 PWM output.

AN6

I Analog Analog input 6.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power.

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 25

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