PIC18F23K22 Datasheet, PDF(150/492 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18F23K22 Datasheet, PDF (150/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18(L)F2X/4XK22

TABLE 10-14: PORTE I/O SUMMARY

Pin

Function

TRIS

Setting

ANSEL

Setting

Pin

Type

Buffer

Type

Description

RE0/P3A/CCP3/AN5 RE0

0

1

O

DIG LATE<0> data output; not affected by analog input.

1

0

I

ST PORTE<0> data input; disabled when analog input

enabled.

P3A(1)

0

CCP3(1)

0

1

O

DIG Enhanced CCP3 PWM output.

1

O

DIG Compare 3 output/PWM 3 output.

1

0

I

ST Capture 3 input.

AN5

1

1

I

AN Analog input 5.

RE1/P3B/AN6

RE1

0

1

1

O

DIG LATE<1> data output; not affected by analog input.

0

I

ST PORTE<1> data input; disabled when analog input

enabled.

P3B

0

AN6

1

x

O

DIG Enhanced CCP3 PWM output.

1

I

AN Analog input 6.

RE2/CCP5/AN7

RE2

0

1

O

DIG LATE<2> data output; not affected by analog input.

1

0

I

ST PORTE<2> data input; disabled when analog input

enabled.

CCP5

0

1

O

DIG Compare 5 output/PWM 5 output.

1

0

I

ST Capture 5 input.

AN7

1

1

I

AN Analog input 7.

RE3/VPP/MCLR

RE3

â

â

I

ST PORTE<3> data input; enabled when Configuration bit

MCLRE = 0.

VPP

â

â

P

AN Programming voltage input; always available

MCLR

â

â

I

ST Active-low Master Clear (device Reset) input; enabled

when configuration bit MCLRE = 1.

Legend:

Note 1:

AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS

= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear..

TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE

Name

Bit 7

ANSELE(1)

â

Bit 6

â

Bit 5

â

Bit 4

â

Bit 3

â

Bit 2

ANSE2

Bit 1

ANSE1

Bit 0

ANSE0

Reset

Values

on page

154

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2

â

TMR0IP

â

RBIP

116

LATE(1)

â

â

â

â

â

LATE2 LATE1 LATE0

155

PORTE

â

â

â

â

RE3

RE2(1)

RE1(1)

RE0(1)

152

SLRCON

â

â

â

SLRE(1) SLRD(1) SLRC

SLRB

SLRA

156

TRISE

WPUE3

â

â

â

â

TRISE2(1) TRISE1(1) TRISE0(1) 154

Legend: â = unimplemented locations, read as â0â. Shaded bits are not used for PORTE.

Note 1: Available on PIC18(L)F4XK22 devices.

DS41412B-page 150

Preliminary

ï£ 2010 Microchip Technology Inc.

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