PIC18F23K22 Datasheet, PDF (55/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
LP, XT, HS
Primary Device Clock
(PRI_IDLE mode)
T1OSC or LFINTOSC⁽¹⁾
HFINTOSC⁽²⁾
None
(Sleep mode)
HSPLL
EC, RC
HFINTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
TCSD⁽¹⁾
TOST⁽³⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
TIOBST⁽⁴⁾
TOST⁽⁴⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
None
TOST⁽³⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
TIOBST⁽⁴⁾
OSTS
IOSF
OSTS
IOSF
OSTS
IOSF
OSTS
IOSF
Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer. t_PLL is the PLL Lock-out Timer.
4: Execution continues during the HFINTOSC stabilization period, TIOBST.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 55