PIC18F23K22 Datasheet, PDF(169/492 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18F23K22 Datasheet, PDF (169/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18(L)F2X/4XK22

FIGURE 12-7:

TMRxGE

TxGPOL

TxGSPM

TxGTM

TxGGO/

DONE

TxG_IN

TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

Set by software

Counting enabled on

rising edge of TxG

Cleared by hardware on

falling edge of TxGVAL

TxCKI

TxGVAL

TIMER1/3/5

TMRxGIF

N

Cleared by software

N+1 N+2 N+3 N+4

Set by hardware on

falling edge of TxGVAL

Cleared by

software

12.12 Peripheral Module Disable

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power con-

sumption to an absolute minimum. Setting the PMD

bits holds the module in Reset and disconnects the

moduleâs clock source. The Module Disable bits for

Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5

(TMR5MD) are in the PMD0 Register. See Section 3.0

âPower-Managed Modesâ for more information.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 169

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