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PIC18F23K22 Datasheet, PDF (148/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
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PIC18(L)F2X/4XK22
TABLE 10-11: PORTD I/O SUMMARY
Pin Name
Function
TRIS
Setting
ANSEL Pin
setting Type
Buffer
Type
Description
RD6/P1C/TX2/CK2/
RD6
0
1
O
DIG LATD<6> data output; not affected by analog input.
AN26
1
0
I
ST PORTD<6> data input; disabled when analog input
enabled.
P1C
0
1
O
DIG Enhanced CCP1 PWM output 3.
TX2
0
1
O
DIG EUSART 2 asynchronous transmit data output.
CK2
0
1
O
DIG EUSART 2 synchronous serial clock output.
1
0
I
ST EUSART 2 synchronous serial clock input.
AN26
1
1
I
AN Analog input 26.
RD7/P1D/RX2/DT2/
RD7
0
1
O
DIG LATD<7> data output; not affected by analog input.
AN27
1
0
I
ST PORTD<7> data input; disabled when analog input
enabled.
P1D
0
1
O
DIG Enhanced CCP1 PWM output 4.
RX2
1
0
I
ST EUSART 2 asynchronous receive data in.
DT2
0
1
O
DIG EUSART 2 synchronous serial data output.
1
0
I
ST EUSART 2 synchronous serial data input.
AN27
1
1
I
AN Analog input 27.
Legend:
Note 1:
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELD(1)
ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1
BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
CCP4CON
LATD(1)
PORTD(1)
—
LATD7
RD7
—
LATD6
RD6
DC4B<1:0>
LATD5 LATD4
RD5
RD4
LATD3
RD3
CCP4M<3:0>
LATD2 LATD1
RD2
RD1
RCSTA2
SLRCON(1)
SPEN RX9 SREN CREN ADDEN FERR OERR
—
—
—
SLRE SLRD SLRC SLRB
SSP2CON1
TRISD(1)
WCOL SSPOV SSPEN CKP
SSPM<3:0>
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.
Note 1: Available on PIC18(L)F4XK22 devices.
Bit 0
Register on
Page
ANSD0
153
ABDEN
274
201
201
201
LATD0
155
RD0
151
RX9D
273
SLRA
156
256
TRISD0
154
TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H MCLRE
—
P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 354
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.
DS41412B-page 148
Preliminary
 2010 Microchip Technology Inc.
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