PIC18F23K22 Datasheet, PDF (333/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

20.0 SR LATCH
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available internally/externally
• Selectable Q and Q output
• Firmware Set and Reset
The SR Latch can be used in a variety of analog
applications, including oscillator circuits, one-shot
circuit, hysteretic controllers, and analog timing
applications.
20.1 Latch Operation
The latch is a Set-Reset Latch that does not depend on
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be set or reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (SYNCC1OUT)
• Comparator C2 output (SYNCC2OUT)
• SRI Pin
• Programmable clock (DIVSRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to set or reset the SR Latch, respectively.
The latch is Reset-dominant. Therefore, if both Set and
Reset inputs are high, the latch will go to the Reset
state. Both the SRPS and SRPR bits are self resetting
which means that a single write to either of the bits is all
that is necessary to complete a latch Set or Reset
operation.
The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR Latch. The output of
either Comparator can be synchronized to the Timer1
clock source. See Section 18.0 “Comparator
Module” and Section 12.0 “Timer1/3/5 Module with
Gate Control” for more information.
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR Latch.
An internal clock source, DIVSRCLK, is available and it
can periodically set or reset the SR Latch. The
SRCLK<2:0> bits in the SRCON0 register are used to
select the clock source period. The SRSCKE and
SRRCKE bits of the SRCON1 register enable the clock
source to set or reset the SR Latch, respectively.
PIC18(L)F2X/4XK22
20.2 Latch Output
The SRQEN and SRNQEN bits of the SRCON0 register
control the Q and Q latch outputs. Both of the SR Latch
outputs may be directly output to I/O pins at the same
time. Control is determined by the state of bits SRQEN
and SRNQEN in the SRCON0 register.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
20.3 DIVSRCLK Clock Generation
The DIVSRCLK clock signal is generated from the
peripheral clock which is pre-scaled by a value
determined by the SRCLK<2:0> bits. See Figure 20-2
and Table for additional detail.
20.4 Effects of a Reset
Upon any device Reset, the SR Latch is not initialized,
and the SRQ and SRNQ outputs are unknown. The
user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 333