PIC18F23K22 Datasheet, PDF (126/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
CCP5IE
CCP4IE
bit 7
R/W-0
CCP3IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP3IE: CCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 9-13: PIE5: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 5
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
TMR6IE
TMR5IE
bit 7
R/W-0
TMR4IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 match interrupt
0 = Disables the TMR6 to PR6 match interrupt
TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enables the TMR5 overflow interrupt
0 = Disables the TMR5 overflow interrupt
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt
DS41412B-page 126
Preliminary
 2010 Microchip Technology Inc.