PIC18F23K22 Datasheet, PDF (201/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CONFIG3H MCLRE
—
P2BMX T3CMX HFOFST CCP3MX PBADEN
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Bit 0
CCP2MX
Register
on Page
354
REGISTER 14-1: CCPxCON: STANDARD CCPx CONTROL REGISTER
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DCxB<1:0>
CCPxM<3:0>
R/W-0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
bit 7-6
bit 5-4
bit 3-0
Unused
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
CCPxM<3:0>: ECCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets the module)
0001 = Reserved
0010 = Compare mode: toggle output on match
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
Note 1:
1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)
1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)
1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,
CCPxIF is set)
1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set)
TimerX (selected by CxTSEL bits) is reset
ADON is set, starting A/D conversion if A/D module is enabled⁽¹⁾
11xx =: PWM mode
This feature is available on CCP5 only.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 201