PIC18F23K22 Datasheet, PDF (457/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 27-20: MASTER SSP I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
102
TR
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1 CB
—
1000
300
300
ns CB is specified to be
ns ^from
ns ^{10 to 400 pF}
103
TF
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1 CB
—
300 ns CB is specified to be
300 ns ^from
100
ns ^{10 to 400 pF}
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms ^{Repeated Start}
ms ^condition
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) —
ms ^{clock pulse is generated}
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
106
THD:DAT Data Input
100 kHz mode
0
—
ns
Hold Time
400 kHz mode
0
0.9 ms
107
TSU:DAT Data Input
100 kHz mode
250
Setup Time
400 kHz mode
100
—
ns (Note 2)
—
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
109
TAA
Output Valid
100 kHz mode
—
3500 ns
from Clock
400 kHz mode
—
1000 ns
1 MHz mode⁽¹⁾
—
— ns
110 TBUF Bus Free Time 100 kHz mode
4.7
400 kHz mode
1.3
— ms Time the bus must be
—
ms ^{free before a new trans-}
mission can start
D102 CB
Bus Capacitive Loading
—
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast mode I²C bus device can be used in a standard mode I²C bus system, but parameter 107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 457