PIC18F23K22 Datasheet, PDF (335/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 20-1:
SRCLK<2:0>
111
110
101
100
011
010
001
000
DIVSRCLK FREQUENCY TABLE
Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz
512
25.6 s
256
12.8 s
128
6.4 s
64
3.2 s
32
1.6 s
16
0.8 s
8
0.4 s
4
0.2 s
32 s
16 s
8 s
4 s
2 s
1 s
0.5 s
0.25 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
0.5 s
128 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
512 s
256 s
128 s
64 s
32 s
16 s
8 s
4 s
REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0
SRLEN
bit 7
R/W-0
R/W-0
SRCLK<2:0>
R/W-0
R/W-0
SRQEN
R/W-0
SRNQEN
R/W-0
SRPS
R/W-0
SRPR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
SRLEN: SR Latch Enable bit⁽¹⁾
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>: SR Latch Clock Divider Bits
000 = Generates a 2 TOSC wide pulse on DIVSRCLK every 4 peripheral clock cycles
001 = Generates a 2 TOSC wide pulse on DIVSRCLK every 8 peripheral clock cycles
010 = Generates a 2 TOSC wide pulse on DIVSRCLK every 16 peripheral clock cycles
011 = Generates a 2 TOSC wide pulse on DIVSRCLK every 32 peripheral clock cycles
100 = Generates a 2 TOSC wide pulse on DIVSRCLK every 64 peripheral clock cycles
101 = Generates a 2 TOSC wide pulse on DIVSRCLK every 128 peripheral clock cycles
110 = Generates a 2 TOSC wide pulse on DIVSRCLK every 256 peripheral clock cycles
111 = Generates a 2 TOSC wide pulse on DIVSRCLK every 512 peripheral clock cycles
SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the SRQ pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the SRNQ pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch bit⁽²⁾
1 = Pulse set input for 2 TOSC clock cycles
0 = No effect on set input
SRPR: Pulse Reset Input of the SR Latch bit⁽²⁾
1 = Pulse reset input for 2 TOSC clock cycles
0 = No effect on Reset input
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
Set only, always reads back ‘0’.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 335