PIC18F23K22 Datasheet, PDF (247/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPxCON2,
set PEN
Falling edge of
9th clock
SCLx
TBRG
SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
SDAx
ACK
TBRG
TBRG
P
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
15.6.10 SLEEP OPERATION
While in Sleep mode, the I²C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSPx interrupt is enabled).
15.6.11 EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates
the current transfer.
15.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSPx module is disabled. Control of the I²C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSPx interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 247