PIC18F23K22 Datasheet, PDF (103/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
EXAMPLE 6-3:
PROGRAM_MEMORY
Required
Sequence
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
DECFSZ COUNTER
; loop until holding registers are full
BRA
WRITE_WORD_TO_HREGS
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DCFSZ
BRA
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER2
WRITE_BYTE_TO_HREGS
INTCON, GIE
EECON1, WREN
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; repeat for remaining write blocks
;
; re-enable interrupts
; disable write to memory
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.4
PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
6.6 Flash Program Operation During
Code Protection
See Section 24.3 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRU
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<21:16>)
—
TBPLTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
—
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
—
TABLAT
Program Memory Table Latch
—
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
115
EECON2
EEPROM Control Register 2 (not a physical register)
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
97
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
HLVDIP TMR3IP CCP2IP
128
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
HLVDIF TMR3IF CCP2IF
119
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCLIE
HLVDIE TMR3IE CCP2IE
124
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 103