PIC18F23K22 Datasheet, PDF (362/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
24.3 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® microcontroller devices.
The user program memory is divided into three or five
blocks, depending on the device. One of these is a
Boot Block of 0.5K or 2K bytes, depending on the
device. The remainder of the memory is divided into
individual blocks on binary boundaries.
Each of the blocks has three code protection bits asso-
ciated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table .
FIGURE 24-2:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F2X/4XK22
MEMORY SIZE/DEVICE
Block Code Protection
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
Controlled By:
(PIC18(L)FX3K22) (PIC18(L)FX4K22) (PIC18(L)FX5K22) (PIC18(L)FX6K22)
Boot Block
(000h-1FFh)
Block 0
(200h-FFFh)
Block 1
(1000h-1FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-1FFFh)
Block 1
(2000h-3FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-1FFFh)
Block 1
(2000h-3FFFh)
Block 2
(4000h-5FFFh)
Block 3
(6000h-7FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-3FFFh)
Block 1
(4000h-7FFFh)
Block 2
(8000h-BFFFh)
Block 3
(C000h-FFFFh)
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
(2000h-1FFFFFh)
Unimplemented
Read ‘0’s
(4000h-1FFFFFh)
Unimplemented Unimplemented
Read ‘0’s
Read ‘0’s
(8000h-1FFFFFh) (10000h-1FFFFFh)
(Unimplemented
Memory Space)
TABLE 24-5: CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION
File Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
300008h CONFIG5L —
—
—
—
300009h CONFIG5H CPD
CPB
—
—
30000Ah CONFIG6L —
—
—
—
30000Bh CONFIG6H WRTD WRTB WRTC⁽²⁾
—
30000Ch CONFIG7L —
—
—
—
30000Dh CONFIG7H — EBTRB
—
—
Legend: Shaded bits are unimplemented.
CP3⁽¹⁾
—
WRT3⁽¹⁾
—
EBTR3⁽¹⁾
—
CP2⁽¹⁾
—
WRT2⁽¹⁾
—
EBTR2⁽¹⁾
—
CP1
—
WRT1
—
EBTR1
—
Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only.
2: In user mode, this bit is read-only and cannot be self-programmed.
Bit 0
CP0
—
WRT0
—
EBTR0
—
DS41412B-page 362
Preliminary
 2010 Microchip Technology Inc.