PIC18F23K22 Datasheet, PDF (271/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
FIGURE 16-5:
RXx/DTx pin
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE
ABDEN
274
BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE
ABDEN
274
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
115
IPR1
—
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
127
IPR3
SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 129
PIE1
—
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
123
PIE3
SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 125
PIR1
—
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
118
PIR3
SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 120
PMD0
UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD
56
RCREG1
EUSART1 Receive Register
—
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
273
RCREG2
EUSART2 Receive Register
—
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
273
SPBRG1
EUSART1 Baud Rate Generator, Low Byte
—
SPBRGH1
EUSART1 Baud Rate Generator, High Byte
—
SPBRG2
EUSART2 Baud Rate Generator, Low Byte
—
SPBRGH2
EUSART2 Baud Rate Generator, High Byte
—
TRISB⁽²⁾
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
154
TRISC
TRISD⁽¹⁾
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
154
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
154
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
272
TXSTA2
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
272
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
Note 1: PIC18(L)F4XK22 devices.
2: PIC18(L)F2XK22 devices.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 271