PIC18F23K22 Datasheet, PDF (221/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
15.4.5 START CONDITION
The I²C specification defines a Start condition as a
transition of SDAx from a high-to -low state while SCLx
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an active state. Figure 15-10 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDAx line low before asserting it
low. This does not conform to the I²C specification that
states no bus collision can occur on a Start.
15.4.6 STOP CONDITION
A Stop condition is a transition of the SDAx line from a
low-to-high state while the SCLx line is high.
Note: At least one SCLx low time must appear
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
15.4.7 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed slave.
Once a slave has been fully addressed, matching both
high and low address bytes, the master can issue a
Restart and the high address byte with the R/W bit set.
The slave logic will then hold the clock and prepare to
clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear, or high
address match fails.
15.4.8 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 15-12: I²C™ START AND STOP CONDITIONS
SDAx
SCLx
S
Start
Condition
Change of
Data Allowed
FIGURE 15-13: I²C™ RESTART CONDITION
Change of
Data Allowed
P
Stop
Condition
Change of
Data Allowed
Sr
Restart
Condition
Change of
Data Allowed
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 221