PIC18F23K22 Datasheet, PDF (260/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
REGISTER 15-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED)
bit 0
DHEN: Data Hold Enable bit (I²C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.
REGISTER 15-5: SSPxMSK: SSPx MASK REGISTER
R/W-1
MSK7
bit 7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-1
bit 0
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPxADD<n> to detect I²C address match
0 = The received address bit n is not used to detect I²C address match
MSK<0>: Mask bit for I²C Slave mode, 10-bit Address
I²C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD<0> to detect I²C address match
0 = The received address bit 0 is not used to detect I²C address match
I²C Slave mode, 7-bit address, the bit is ignored
DS41412B-page 260
Preliminary
 2010 Microchip Technology Inc.