PIC18F23K22 Datasheet, PDF (183/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP TMR1IP
127
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP CCP2IP
128
IPR4
—
—
—
—
—
CCP5IP
CCP4IP CCP3IP
130
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE TMR1IE
123
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE CCP2IE
124
PIE4
—
—
—
—
—
CCP5IE
CCP4IE CCP3IE
126
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF TMR1IF
118
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF CCP2IF
119
PIR4
—
—
—
—
—
CCP5IF
CCP4IF CCP3IF
121
PMD0
UART2MD UART1MD TMR6MD TMR5MD
TMR4MD
TMR3MD TMR2MD TMR1MD
56
PMD1
MSSP2MD MSSP1MD
—
CCP5MD
CCP4MD
CCP3MD CCP2MD CCP1MD
57
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1SOSCEN T1SYNC T1RD16 TMR1ON 170
T1GCON
TMR1GE T1GPOL
T1GTM T1GSPM T1GGO/DONE T1GVAL
T1GSS
171
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
T3SOSCEN T3SYNC T3RD16 TMR3ON 170
T3GCON
TMR3GE T3GPOL
T3GTM T3GSPM T3GGO/DONE T3GVAL
T3GSS
171
T5CON
TMR5CS<1:0>
T5CKPS<1:0>
T5SOSCEN T5SYNC T5RD16 TMR5ON 170
T5GCON
TMR5GE T5GPOL
T5GTM T5GSPM T5GGO/DONE T5GVAL
T5GSS
171
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
—
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
—
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
—
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
—
TMR5L
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
—
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1 TRISA0
154
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1 TRISB0
154
TRISC
TRISD⁽¹⁾
TRISE
TRISC7
TRISD7
WPUE3
TRISC6
TRISD6
—
TRISC5
TRISD5
—
TRISC4
TRISD4
—
TRISC3
TRISD3
—
TRISC2
TRISC1 TRISC0
154
TRISD2
TRISD1 TRISD0
154
TRISE2⁽¹⁾ TRISE1⁽¹⁾ TRISE0⁽¹⁾ 154
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.
TABLE 14-6: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CONFIG3H MCLRE
—
P2BMX T3CMX HFOFST CCP3MX PBADEN
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Bit 0
CCP2MX
Register
on Page
354
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 183