PIC18F23K22 Datasheet, PDF (114/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the Global Interrupt Enable bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
FIGURE 9-1:
PIC18 INTERRUPT LOGIC
PIR1<6:0>
PIE1<6:0>
IPR1<6:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
PIR4<2:0>
PIE4<2:0>
IPR4<2:0>
PIR5<2:0>
PIE5<2:0>
IPR5<2:0>
High Priority Interrupt Generation
Low Priority Interrupt Generation
PIR1<6:0>
PIE1<6:0>
IPR1<6:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
PIR4<2:0>
PIE4<2:0>
IPR4<2:0>
PIR5<2:0>
PIE5<2:0>
IPR5<2:0>
INT0IF
INT0IE
TMR0IF
TMR0IE
TMR0IP
RBIF
(1)
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
IPEN
IPEN
GIEL/PEIE
IPEN
TMR0IF
TMR0IE
TMR0IP
(1)
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Note 1: The RBIF interrupt also requires the individual pin IOCB enables.
Wake-up if in
Idle or Sleep modes
Interrupt to CPU
Vector to Location
0008h
GIEH/GIE
Interrupt to CPU
Vector to Location
0018h
GIEH/GIE
GIEL/PEIE
DS41412B-page 114
Preliminary
 2010 Microchip Technology Inc.