PIC18F23K22 Datasheet, PDF(187/492 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18F23K22 Datasheet, PDF (187/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18(L)F2X/4XK22

TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register

on Page

CCP1CON

P1M<1:0>

DC1B<1:0>

CCP1M<3:0>

201

CCP2CON

P2M<1:0>

DC2B<1:0>

CCP2M<3:0>

201

CCP3CON

P3M<1:0>

DC3B<1:0>

CCP3M<3:0>

201

CCP4CON

â

â

DC4B<1:0>

CCP4M<3:0>

201

CCP5CON

â

â

DC5B<1:0>

CCP5M<3:0>

201

CCPTMRS0

C3TSEL<1:0>

â

C2TSEL<1:0>

â

C1TSEL<1:0>

204

CCPTMRS1

â

â

â

â

C5TSEL<1:0>

C4TSEL<1:0>

204

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

115

IPR1

â

ADIP

RC1IP

TX1IP

SSP1IP

CCP1IP

TMR2IP TMR1IP

127

IPR2

OSCFIP

C1IP

C2IP

EEIP

BCL1IP

HLVDIP

TMR3IP CCP2IP

128

IPR4

â

â

â

â

â

CCP5IP

CCP4IP CCP3IP

129

PIE1

â

ADIE

RC1IE

TX1IE

SSP1IE

CCP1IE TMR2IE TMR1IE 123

PIE2

OSCFIE

C1IE

C2IE

EEIE

BCL1IE

HLVDIE

TMR3IE CCP2IE

124

PIE4

â

â

â

â

â

CCP5IE

CCP4IE CCP3IE

126

PIR1

â

ADIF

RC1IF

TX1IF

SSP1IF

CCP1IF

TMR2IF TMR1IF

118

PIR2

OSCFIF

C1IF

C2IF

EEIF

BCL1IF

HLVDIF

TMR3IF CCP2IF

119

PIR4

â

â

â

â

â

CCP5IF

CCP4IF CCP3IF

121

PMD0

UART2MD UART1MD TMR6MD TMR5MD

TMR4MD

TMR3MD TMR2MD TMR1MD 56

PMD1

MSSP2MD MSSP1MD

â

CCP5MD

CCP4MD

CCP3MD CCP2MD CCP1MD 57

PR2

Timer2 Period Register

â

PR4

Timer4 Period Register

â

PR6

Timer6 Period Register

â

T2CON

â

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

170

T4CON

â

T4OUTPS<3:0>

TMR4ON

T4CKPS<1:0>

170

T6CON

â

T6OUTPS<3:0>

TMR6ON

T6CKPS<1:0>

170

TMR2

Timer2 Period Register

â

TMR4

Timer4 Period Register

â

TMR6

Timer6 Period Register

â

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1 TRISB0

154

TRISC

TRISD(1)

TRISE

TRISC7

TRISD7

WPUE3

TRISC6

TRISD6

â

TRISC5

TRISD5

â

TRISC4

TRISD4

â

TRISC3

TRISD3

â

TRISC2

TRISC1 TRISC0

154

TRISD2

TRISD1 TRISD0

154

TRISE2(1) TRISE1(1) TRISE0(1) 154

Legend: â = Unimplemented location, read as â0â. Shaded bits are not used by Capture mode.

Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.

TABLE 14-11: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

CONFIG3H MCLRE

â

P2BMX T3CMX HFOFST CCP3MX PBADEN

Legend: â = Unimplemented location, read as â0â. Shaded bits are not used by Capture mode.

Bit 0

CCP2MX

Register

on Page

354

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 187

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