PIC18F23K22 Datasheet, PDF(141/492 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18F23K22 Datasheet, PDF (141/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

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PIC18(L)F2X/4XK22

TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)

Pin

Function

TRIS ANSEL

Setting Setting

Pin

Type

Buffer

Type

Description

RB6/KBI2/PGC

RB6

0

1

O

DIG LATB<6> data output; not affected by analog input.

1

0

I

ST PORTB<6> data input; disabled when analog input

enabled.

IOC2

1

0

I

TTL Interrupt-on-change pin.

TX2(3)

0

1

O

DIG EUSART 2 asynchronous transmit data output.

CK2(3)

0

1

O

DIG EUSART 2 synchronous serial clock output.

1

0

I

ST EUSART 2 synchronous serial clock input.

PGC

x

x

I

ST In-Circuit Debugger and ICSPTM programming clock input.

RB7/KBI3/PGD

RB7

0

1

O

DIG LATB<7> data output; not affected by analog input.

1

0

I

ST PORTB<7> data input; disabled when analog input

enabled.

IOC3

1

0

I

TTL Interrupt-on-change pin.

RX2(2), (3)

1

0

I

ST EUSART 2 asynchronous receive data input.

DT2(2), (3)

0

1

O

DIG EUSART 2 synchronous serial data output.

1

0

I

ST EUSART 2 synchronous serial data input.

PGD

x

x

O

DIG In-Circuit Debugger and ICSPTM programming data output.

x

x

I

ST In-Circuit Debugger and ICSPTM programming data input.

Legend:

Note 1:

2:

3:

AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

TABLE 10-6: REGISTERS ASSOCIATED WITH PORTB

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register

on Page

ANSELB

â

â

ANSB5

ANSB4

ANSB3

ANSB2 ANSB1 ANSB0

153

ECCP2AS CCP2ASE

CCP2AS<2:0>

P2SSAC<1:0>

P2SSBD<1:0>

205

CCP2CON

P2M<1:0>

DC2B<1:0>

CCP2M<3:0>

201

ECCP3AS CCP3ASE

CCP3AS<2:0>

P3SSAC<1:0>

P3SSBD<1:0>

205

CCP3CON

P3M<1:0>

DC3B<1:0>

CCP3M<3:0>

201

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF RBIF

115

INTCON2

RBPU INTEDG0 INTEDG1 INTEDG2

â

TMR0IP

â

RBIP

116

INTCON3

INT2IP INT1IP

â

INT2IE

INT1IE

â

INT2IF INT1IF

117

IOCB

IOCB7

IOCB6

IOCB5

IOCB4

â

â

â

â

156

LATB

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2 LATB1 LATB0

155

PORTB

RB7

RB6

SLRCON

â

â

RB5

â

RB4

SLRE(1)

RB3

SLRD(1)

RB2

RB1

RB0

151

SLRC

SLRB

SLRA

156

T1GCON

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL

T1GSS<1:0>

171

T3CON

TMR3CS<1:0>

T3CKPS<1:0>

T3SOSCEN T3SYNC T3RD16 TMR3ON 170

T5GCON

TMR5GE T5GPOL T5GTM T5GSPM T5GGO_DONE T5GVAL

T5GSS

171

TRISB

TRISB7 TRISB6 TRISB5 TRISB4

TRISB3

TRISB2 TRISB1 TRISB0 154

WPUB

WPUB7 WPUB6 WPUB5 WPUB4

WPUB3

WPUB2 WPUB1 WPUB0 155

Legend: â = unimplemented locations, read as â0â. Shaded bits are not used for PORTB.

Note 1: Available on PIC18(L)F4XK22 devices.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 141

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