PIC18F23K22 Datasheet, PDF (135/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 10-1: PORTA I/O SUMMARY (CONTINUED)
Pin Name
Function
TRIS ANSEL
Setting Setting
Pin
Type
Buffer
Type
Description
RA6/CLKO/OSC2
RA6
0
1
O
DIG LATA<6> data output; enabled in INTOSC modes when
CLKO is not enabled.
1
0
I
TTL PORTA<6> data input; enabled in INTOSC modes when
CLKO is not enabled.
CLKO
x
1
O
DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
OSC2
x
x
O XTAL Oscillator crystal output; connects to crystal or resonator in
Crystal Oscillator mode.
RA7/CLKI/OSC1
RA7
0
1
O
DIG LATA<7> data output; disabled in external oscillator modes.
1
0
I
TTL PORTA<7> data input; disabled in external oscillator
modes.
CLKI
x
1
I
AN External clock source input; always associated with pin
function OSC1.
OSC1
x
x
I XTAL Oscillator crystal input or external clock source input ST
buffer when configured in RC mode; CMOS otherwise.
Legend:
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I²C^TM = Schmitt Trigger input with
I²C.
TABLE 10-2: REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
ANSA5
—
ANSA3 ANSA2 ANSA1 ANSA0
152
CM1CON0
C1ON C1OUT C1OE C1POL C1SP
C1R
C1CH<1:0>
310
CM2CON0
C2ON C2OUT C2OE C2POL C2SP
C2R
C2CH<1:0>
311
VREFCON1 DACEN DACLPS DACOE —
DACPSS<1:0>
— DACNSS 341
VREFCON2
—
—
—
DACR<4:0>
342
HLVDCON VDIRMAG BGVST IRVST HLVDEN
HLVDL<3:0>
343
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
151
SLRCON
—
—
—
SLRE SLRD
SLRC
SLRB SLRA
156
SRCON0
SRLEN
SRCLK<2:0>
SRQEN SRNQEN SRPS SRPR
335
SSP1CON1 WCOL SSPOV SSPEN CKP
SSPM<3:0>
256
T0CON
TMR0ON T08BIT T0CS T0SE PSA
T0PS<2:0>
157
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 154
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA.
TABLE 10-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CONFIG1H IESO FCMEN PRICLKEN PLLCFG
FOSC<3:0>
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA.
Bit 0
Register
on Page
351
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 135