PIC18F23K22 Datasheet, PDF (258/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
REGISTER 15-3: SSPxCON2: SSPx CONTROL REGISTER 2
R/W-0
GCEN
bit 7
R-0
ACKSTAT
R/W-0
ACKDT
R/S/HC-0
ACKEN⁽¹⁾
R/S/HC-0
RCEN⁽¹⁾
R/S/HC-0
PEN⁽¹⁾
R/S/HC-0
RSEN⁽¹⁾
R/W/HC-0
SEN⁽¹⁾
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN: General Call Enable bit (in I²C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I²C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
ACKDT: Acknowledge Data bit (in I²C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
ACKEN⁽¹⁾: Acknowledge Sequence Enable bit (in I²C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
RCEN⁽¹⁾: Receive Enable bit (in I²C Master mode only)
1 = Enables Receive mode for I²C
0 = Receive idle
PEN⁽¹⁾: Stop Condition Enable bit (in I²C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN⁽¹⁾: Repeated Start Condition Enabled bit (in I²C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN⁽¹⁾: Start Condition Enabled bit (in I²C Master mode only)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
DS41412B-page 258
Preliminary
 2010 Microchip Technology Inc.