PIC18F23K22 Datasheet, PDF (354/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1
U-0
R/P-1
R/P-1
R/P-1
R/P-1
MCLRE
—
P2BMX
T3CMX
HFOFST CCP3MX
bit 7
R/P-1
PBADEN
R/P-1
CCP2MX
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
P2BMX: P2B Input MUX bit
1 = P2B is on RB5⁽¹⁾
P2B is on RD2⁽²⁾
0 = P2B is on RC0
T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5
HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize
0 = The system clock is held off until the HFINTOSC is stable
CCP3MX: CCP3 MUX bit
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RC6⁽¹⁾
CCP3 input/output is multiplexed with RE0⁽²⁾
PBADEN: PORTB A/D Enable bit
1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset
0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset
CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
PIC18(L)F2XK22 devices only.
PIC18(L)F4XK22 devices only.
DS41412B-page 354
Preliminary
 2010 Microchip Technology Inc.