PIC18F23K22 Datasheet, PDF (165/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

12.7.2.3 Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1/3/5 Gate Control.
The Comparator 1 output (SYNCC1OUT) can be
synchronized to the Timer1/3/5 clock or left
asynchronous. For more information see Section 18.8.4
“Synchronizing Comparator Output to Timer1”.
12.7.2.4 Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1/3/5 Gate
Control. The Comparator 2 output (SYNCC2OUT) can
be synchronized to the Timer1/3/5 clock or left
asynchronous. For more information see
Section 18.8.4 “Synchronizing Comparator Output
to Timer1”.
12.7.3 TIMER1/3/5 GATE TOGGLE MODE
When Timer1/3/5 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1/3/5 gate signal, as opposed to the duration of a
single level pulse.
The Timer1/3/5 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 12-5 for timing details.
Timer1/3/5 Gate Toggle mode is enabled by setting the
TxGTM bit of the TxGCON register. When the TxGTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
Enabling Toggle mode at the same time as
changing the gate polarity may result in
indeterminate operation.
PIC18(L)F2X/4XK22
12.7.4 TIMER1/3/5 GATE SINGLE-PULSE
MODE
When Timer1/3/5 Gate Single-Pulse mode is enabled,
it is possible to capture a single-pulse gate event.
Timer1/3/5 Gate Single-Pulse mode is first enabled by
setting the TxGSPM bit in the TxGCON register. Next,
the TxGGO/DONE bit in the TxGCON register must be
set. The Timer1/3/5 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the TxGGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1/3/5 until the TxGGO/DONE bit is
once again set in software.
Clearing the TxGSPM bit of the TxGCON register will
also clear the TxGGO/DONE bit. See Figure 12-6 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3/5
Gate source to be measured. See Figure 12-7 for
timing details.
12.7.5 TIMER1/3/5 GATE VALUE STATUS
When Timer1/3/5 Gate Value Status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the TxGVAL bit in
the TxGCON register. The TxGVAL bit is valid even
when the Timer1/3/5 Gate is not enabled (TMRxGE bit
is cleared).
12.7.6 TIMER1/3/5 GATE EVENT
INTERRUPT
When Timer1/3/5 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIR3 register will be
set. If the TMRxGIE bit in the PIE3 register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer1/3/5 Gate is not enabled (TMRxGE bit is
cleared).
For more information on selecting high or low priority
status for the Timer1/3/5 Gate Event Interrupt see
Section 9.0 “Interrupts”.
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 165