PIC18F23K22 Datasheet, PDF (360/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
24.2 Watchdog Timer (WDT)
For PIC18(L)F2X/4XK22 devices, the WDT is driven by
the LFINTOSC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the LFINTOSC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits of
the OSCCON register clears the WDT
and postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
FIGURE 24-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
LFINTOSC Source
Enable WDT
WDT Counter
128
Change on IRCF bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Programmable Postscaler ^Reset
1:1 to 1:32,768
4
Wake-up
from Power
Managed Modes
WDT
Reset
DS41412B-page 360
Preliminary
 2010 Microchip Technology Inc.