PIC18F23K22 Datasheet, PDF (452/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS  to SCK  or SCK  Input
TssL2scL
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
73A Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
75
TdoR
SDO Data Output Rise Time
76
TdoF
SDO Data Output Fall Time
77
TssH2doZ SS to SDO Output High-Impedance
78
TscR
SCK Output Rise Time (Master mode)
79
TscF
SCK Output Fall Time (Master mode)
80
TscH2doV, SDO Data Output Valid after SCK Edge
TscL2doV
83
TscH2ssH, SS  after SCK edge
TscL2ssH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
TCY
— ns
1.25 TCY + 30 —
40
—
1.25 TCY + 30 —
40
—
100
—
ns
ns (Note 1)
ns
ns (Note 1)
ns
1.5 TCY + 40 —
100
—
ns (Note 2)
ns
—
25 ns
—
25 ns
10
50 ns
—
25 ns
—
25 ns
—
50 ns
1.5 TCY + 40 — ns
FIGURE 27-13:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 27-3 for load conditions.
DS41412B-page 452
Preliminary
 2010 Microchip Technology Inc.