PIC18F23K22 Datasheet, PDF (67/492 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

PIC18(L)F2X/4XK22
4.6 Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used by software to determine the
nature of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. The table identifies
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear, WDT Resets, STKFUL, STKUNF, etc.).
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition
Program
Counter
SBOREN
RCON Register
STKPTR Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
1
11100
0
0
RESET Instruction
0000h
u⁽²⁾
0uuuu
u
u
Brown-out Reset
0000h
u⁽²⁾
111u0
u
u
MCLR during Power-Managed
0000h
u⁽²⁾
u1uuu
u
u
Run Modes
MCLR during Power-Managed
0000h
u⁽²⁾
u10uu
u
u
Idle Modes and Sleep Mode
WDT Time-out during Full Power 0000h
u⁽²⁾
u0uuu
u
u
or Power-Managed Run Mode
MCLR during Full Power
Execution
0000h
u⁽²⁾
uuuuu
u
u
Stack Full Reset (STVREN = 1)
0000h
u⁽²⁾
uuuuu
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u⁽²⁾
uuuuu
u
1
Stack Underflow Error (not an
0000h
u⁽²⁾
uuuuu
u
1
actual Reset, STVREN = 0)
WDT Time-out during
PC + 2
u⁽²⁾
u00uu
u
u
Power-Managed Idle or Sleep
Modes
Interrupt Exit from
Power-Managed Modes
PC + 2⁽¹⁾
u⁽²⁾
uu0uu
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
TABLE 4-4: REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
RCON
IPEN SBOREN
—
RI
TO
PD
POR
STKPTR STKFUL STKUNF
—
STKPTR<4:0>
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.
Bit 0
BOR
Register
on Page
60
72
 2010 Microchip Technology Inc.
Preliminary
DS41412B-page 67