AMD-K6 Datasheet, PDF (98/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
5.2
A[31:3] (Address Bus)
Summary
Driven, Sampled, and
Floated
A[31:5] Bidirectional, A[4:3] Output
A[31:3] contain the physical address for the current bus cycle.
The processor drives addresses on A[31:3] during memory and
I/O cycles, and cycle definition information during special bus
cycles. The processor samples addresses on A[31:5] during
inquire cycles.
As Outputs: A[31:3] are driven valid off the same clock edge as
ADS # and remain in the same state until the clock edge on
which NA# or the last expected BRDY# of the cycle is sampled
asserted. A[31:3] are driven during memory cycles, I/O cycles,
special bus cycles, and interrupt acknowledge cycles. The
processor continues to drive the address bus while the bus is
idle.
As Inputs: The processor samples A[31:5] during inquire cycles
on the clock edge on which EADS# is sampled asserted. Even
though A4 and A3 are not used during the inquire cycle, they
must be driven to a valid state and must meet the same timings
as A[31:5].
A[31:3] are floated off the clock edge that AHOLD or BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
The processor resumes driving A[31:3] off the clock edge on
which the processor samples AHOLD or BOFF # negated and off
the clock edge on which the processor negates HLDA.
80
Signal Descriptions
Chapter 5