AMD-K6 Datasheet, PDF (256/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
15.2
I/O Buffer Model
AMD provides models of the AMD-K6 processor I/O buffers for
system designers to use in board-level simulations. These I/O
buffer models conform to the I/O Buffer Information
Specification (IBIS), Version 2.1. The Standard I/O Model uses
K6STD, the standard I/O buffer representation, for all I/O
buffers. The Strong I/O Model uses K6STG, the stronger I/O
buffer representation for A[20:3], ADS#, HITM#, and W/R#,
and uses K6STD for the remainder of the I/O buffers.
Both I/O models contain voltage versus current (V/I) and
voltage versus time (V/T) data tables for accurate modeling of
I/O buffer behavior.
The following list characterizes the properties of each I/O
buffer model:
s All data tables contain minimum, typical, and maximum
values to allow for worst-case, typical, and best-case
simulations, respectively.
s The pullup, pulldown, power clamp, and ground clamp
device V/I tables contain enough data points to accurately
represent the nonlinear nature of the V/I curves. In addition,
the voltage ranges provided in these tables extend beyond
the normal operating range of the AMD-K6 processor for
those simulators that yield more accurate results based on
this wider range. Figure 80 and Figure 81 on page 239
illustrate the min/typ/max pulldown and pullup V/I curves
for K6STD between 0V and 3.3V.
s The rising and falling ramp rates are specified.
s The min/typ/max V_CC3 operating range is specified as
3.135V, 3.3V, and 3.6V, respectively.
s V_il = 0.8V, V_ih = 2.0V, and V_meas = 1.5V
s The R/L/C of the package is modeled.
s The capacitance of the silicon die is modeled.
s The model assumes the test load is 0 capacitance, resistance,
inductance, and voltage.
238
I/O Buffer Characteristics
Chapter 15