AMD-K6 Datasheet, PDF (126/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
5.37
Summary
Driven
PCHK# (Parity Check)
Output
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle. (Even parity means that the total number of 1 bits
within each byte of data and its respective data parity bit is
even.) The processor checks data parity for the data bytes that
are valid, as defined by BE[7:0]#, the byte enables.
PCHK# is always driven but is only asserted for memory and I/O
read bus cycles and the second cycle of an interrupt
acknowledge sequence. PCHK# is not driven during any type of
write cycles or special bus cycles. The processor does not take
an internal exception as the result of detecting a data parity
error, and system logic must respond appropriately to the
assertion of this signal.
The processor ensures that PCHK# does not glitch, enabling the
signal to be used as a clocking source for system logic.
PCHK# is always driven except in Tri-State Test mode. For each
BRDY# returned to the processor during a read cycle with a
parity error detected on the data bus, PCHK# is asserted for
one clock, one clock edge after BRDY# is sampled asserted.
108
Signal Descriptions
Chapter 5