AMD-K6 Datasheet, PDF (35/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
RISC86 #0
From Decode Logic
RISC86 #1 RISC86 #2
RISC86 #3
Centralized RISC86^®
Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure 5. AMD-K6^® Processor Scheduler
2.6
Execution Units
The AMD-K6 processor contains seven execution units—store,
load, integer X, integer Y, multimedia, floating-point, and
branch condition. Each unit is independent and capable of
handling the RISC86 operations. Table 1 on page 18 details the
execution units, functions performed within these units,
operation latency, and operation throughput.
The store and load execution units are two-staged pipelined
designs. The store unit performs data writes and register
calculation for LEA/PUSH. Data memory and register writes
from stores are available after one clock. The load unit
performs data memory reads. Data is available from the load
unit after two clocks.
The Integer X execution unit can operate on all ALU
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
Chapter 2
Internal Architecture
17