AMD-K6 Datasheet, PDF (205/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
8.11
8.12
Writethrough vs. Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6 processor L1
data cache. The following conditions apply to both the
writethrough and writeback modes:
s Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
• An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
• An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
s Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
• Shared MESI lines are in the writethrough state.
• Modified and exclusive MESI lines are in the writeback
state.
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in Real
mode. The CPU applies the A20M# masking to its tags, through
which all programs access the caches. Therefore, assertion of
A20M# affects all addresses (cache and external memory),
including the following:
s Cache-line fills (caused by read misses)
s Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
s Internal snoops
s Inquire cycles
s The FLUSH# signal
s The WBINVD instruction
Chapter 8
Cache Organization
187