AMD-K6 Datasheet, PDF (146/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Misaligned
Single-Transfer
Memory Read and
Write
Figure 46 on page 129 shows a misaligned (split) memory read
followed by a misaligned memory write. Any cycle that is not
aligned as defined in “SCYC (Split Cycle)” on page 111 is
considered misaligned. When the processor encounters a
misaligned access, it determines the appropriate pair of bus
cycles — each with its own ADS# and BRDY# — required to
complete the access.
The AMD-K6 processor performs misaligned memory reads and
memory writes using least-significant bytes (LSBs) first
followed by most-significant bytes (MSBs). Table 20 shows the
order. In the first memory read cycle in Figure 46, the processor
reads the least-significant bytes. Immediately after the
processor samples BRDY# asserted, it drives the second bus
cycle to read the most-significant bytes to complete the
misaligned transfer.
Table 20. Bus-Cycle Order During Misaligned Transfers
Type of Access
Memory Read
Memory Write
First Cycle
LSBs
LSBs
Second Cycle
MSBs
MSBs
Similarly, the misaligned memory write cycle in Figure 46
transfers the LSBs to the memory bus first. In the next cycle,
after the processor samples BRDY# asserted, the MSBs are
written to the memory bus.
128
Bus Cycles
Chapter 6