AMD-K6 Datasheet, PDF (198/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
write allocations between 640 Kbytes and 1 Mbyte (000A_0000h
to 000F_FFFFh) because it is considered a non-cacheable
region of memory.
Figure 70 shows the logic flow for all the mechanisms involved
with write allocate for memory bus cycles. The left side of the
diagram (the text) describes the conditions that need to be true
in order for the value of that line to be a 1. Items 1 to 3 of the
diagram are related to general cache operation and items 4 to
11 are related to the write allocate mechanisms.
For more information about write allocate, see the
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326.
1) CD Bit of CR0.
2) PCD Signal
3) CI Bit of TR12
4) Write to Cacheable Page (CCR)
5) Write to a Sector
6) WCDE Bit
7) Less Than Limit (WAELIM)
8) Between 640 Kbytes and 1 Mbyte
9) Between 15–16 Mbytes
10) Write Allocate Enable 15–16 Mbyte (WAE15M)
Perform
Write Allocate
Figure 70. Write Allocate Logic Mechanisms and Conditions
Descriptions of the
Logic Mechanisms
and Conditions
180
1. CD Bit of CR0—When the cache disable (CD) bit within
control register 0 (CR0) is set to 1, the cache fill mechanism
for both reads and writes is disabled, therefore write
allocate does not occur.
2. PCD Signal—When the PCD (page cache disable) signal is
driven High, caching for that page is disabled even if KEN#
is sampled asserted, therefore write allocate does not occur.
3. CI Bit of TR12—When the cache inhibit bit of Test Register
12 is set to 1, the L1 caches are disabled, therefore write
allocate does not occur.
4. Write to a Cacheable Page (CCR)—A write allocate is
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last cache
fill for a read miss. See “Write to a Cacheable Page” on page
178 for a detailed description of this condition.
Cache Organization
Chapter 8