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AMD-K6 Datasheet, PDF (224/346 Pages) Advanced Micro Devices – AMD-K6 Processor | |||
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AMD-K6® Processor Data Sheet
Preliminary Information
20695H/0âMarch 1998
TAP Registers
206
the state transitions of the TAP controller to occur. TCK can
be stopped in the logic 0 or 1 state.
s TDIâThe Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
s TDOâThe Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
s TMSâThe Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
s TRST#âThe Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Refer to âElectrical Dataâ on page 233 and âSignal Switching
Characteristicsâ on page 241 to obtain the electrical
specifications of the test signals.
The AMD-K6 processor provides an Instruction Register (IR)
and three Test Data Registers (TDR) to support the
boundary-scan architecture. The IR and one of the TDRsâthe
Boundary-Scan Register (BSR)âconsist of a shift register and
an output register. The shift register is loaded in parallel in the
Capture states. (See âTAP Controller State Machineâ on page
212 for a description of the TAP controller states.) In addition,
the shift register is loaded and shifted serially in the Shift
states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
s 01bâLoaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
s 000bâLoaded into the three most significant bits
Test and Debug
Chapter 11
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