AMD-K6 Datasheet, PDF (135/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Table 14. Input Pin Types
Name
Type
Note
Name
Type
Note
A20M#
Asynchronous
Note 1 IGNNE#
Asynchronous
Note 1
AHOLD
Synchronous
INIT
Asynchronous
Note 2
BF[2:0]
Synchronous
Note 4 INTR
Asynchronous
Note 1
BOFF#
Synchronous
INV
Synchronous
BRDY#
Synchronous
KEN#
Synchronous
BRDYC#
Synchronous
Note 7 NA#
Synchronous
CLK
Clock
NMI
Asynchronous
Note 2
EADS#
Synchronous
RESET
Asynchronous
Note 5, 6
EWBE#
Synchronous
SMI#
Asynchronous
Note 2
FLUSH#
Asynchronous
Note 2, 3 STPCLK#
Asynchronous
Note 1
HOLD
Synchronous
WB/WT#
Synchronous
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is
sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the
negation of RESET.
4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold
time of two clocks relative to the negation of RESET.
5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V_CC reach
specification before it is negated.
6. During a warm reset, while CLK and V_CC are within their specification, RESET must remain asserted for a minimum of 15 clocks
prior to its negation.
7. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC# must meet the specified
hold time relative to the negation of RESET. If asserted asynchronously, BRDYC# must meet a minimum setup and hold time of
two clocks relative to the negation of RESET.
Chapter 5
Signal Descriptions
117