AMD-K6 Datasheet, PDF (234/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
system logic, including the execution of writeback cycles when
a modified cache line is hit.
While the L1 is inhibited, the processor continues to drive the
PCD output signal appropriately, which system logic can use to
control external L2 caching.
In order to completely disable the L1 cache so no valid lines
exist in the cache, the Cache Inhibit bit must be set to 1 and
the cache must be flushed in one of the following ways:
s By asserting the FLUSH# input signal
s By executing the WBINVD instruction
s By executing the INVD instruction (modified cache lines are
not written back to memory)
11.5
Debug
Debug Registers
The AMD-K6 processor implements the standard x86 debug
functions, registers, and exceptions. In addition, the processor
supports the I/O breakpoint debug extension. The debug
feature assists programmers and system designers during
software execution tracing by generating exceptions when one
or more events occur during processor execution. The
exception handler, or debugger, can be written to perform
various tasks, such as displaying the conditions that caused the
breakpoint to occur, displaying and modifying register or
memory contents, or single-stepping through program
execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
Figures 74 through 77 show the 32-bit debug registers
supported by the processor.
216
Test and Debug
Chapter 11